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1
Step-by-step Functional Verification with SystemVerilog and OVM

Step-by-step Functional Verification with SystemVerilog and OVM

Sasan Iman
年:
2008
语言:
english
文件:
PDF, 26.37 MB
0 / 0
english, 2008
2
Logic synthesis for low power VLSI designs

Logic synthesis for low power VLSI designs

Iman, Sasan, Pedram, Massoud
年:
1998
语言:
english
文件:
PDF, 96.89 MB
0 / 0
english, 1998
3
Logic Synthesis for Low Power VLSI Designs

Logic Synthesis for Low Power VLSI Designs

Iman, Sasan, Pedram, Massoud
年:
1998
语言:
english
文件:
PDF, 96.89 MB
0 / 4.0
english, 1998
4
Logic Synthesis for Low Power VLSI Designs

Logic Synthesis for Low Power VLSI Designs

Sasan Iman, Massoud Pedram (auth.)
年:
1998
语言:
english
文件:
PDF, 7.11 MB
0 / 0
english, 1998
5
The e-Hardware Verification Language (Information Technology: Transmission, Processing and Storage)

The e-Hardware Verification Language (Information Technology: Transmission, Processing and Storage)

Sasan Iman, Sunita Joshi
年:
2004
语言:
english
文件:
PDF, 6.97 MB
0 / 0
english, 2004
6
The E hardware verification language

The E hardware verification language

Sasan Iman, Sunita Joshi
年:
2004
语言:
english
文件:
PDF, 7.60 MB
0 / 0
english, 2004